This information is presented in an attempt to jumpstart engineers learning ATA for the first time, and as a ready reference.
ATA is a wonderfully frustrating mix of historical practice and specifications. Parallel ATA (PATA) requires an OS driver to manipulate signals on an electrical bus. Serial ATA (SATA) requires an OS driver to function at a much higher level, basically sending packets containing ATA commands and data.
At a command set level, one must work with two or more command sets: basic ATA commands. ATAPI commands ("mostly SCSI/MMC"). true SCSI commands. Each command set is associated with a class of devices. The ATA command set is fairly well documented. ATAPI, on the other hand, is not. Occasionally you must find yourself digging into long-withdrawn (out-of-print) specifications for the reason behind a device's behavior.
BIG FAT BROKEN LINKS WARNING
Some of the links on this page are broken, due to T10 or T13 shuffling.
Assistance in finding better, hopefully-permanent links for these critical resources would be greatly appreciated. (delete this wiki section when work is complete)
ATA command set
First we start with the basic ATA specifications, in descending order. These are all are found on the home of ATA, the T13 committee website. For the most recent specification, a project draft is presented. For the case of ratified standards, the last draft is presented. In the latter case, the official standards require a fee for online viewing and are thus avoided.
- ATA/ATAPI-7: vol. 1, vol. 2, vol. 3
- ATA/ATAPI-6: spec
- ATA/ATAPI-5: spec, proposed errata.
- ATA/ATAPI-4: spec, errata.
- ATA-3: (withdrawn 2002): spec
- ATA-2: (withdrawn 2001): spec
- ATA-1: (withdrawn 1999): spec
In addition to the command set, these documents also describe PATA protocols and electrical specification, and begin (in ATA/ATAPI-7) to describe SATA. At the present time, it is recommended that Serial ATA developers also study documents at www.sata-io.org in depth.
Serial ATA (SATA) extensions
Most of the new ATA technology being developed today is based on Serial ATA. A starting point for engineers and non-engineers alike is www.sata-io.org. The SATA technology page links to several technical resources, particularly the specifications and design guide pages.
The SATA 1.0a spec is the basic SATA spec. This information trickles down into ATA/ATAPI-7, but the SATA specification here is usually more current. Note that the 1.0a PDF file takes an abnormally long time to open on some PDF readers, so be patient. It could take 10-20 minutes to open the PDF files. Once the PDF file is opened, however, viewing proceeds at a reasonable pace.
The next revision of SATA, SATA II, can be found in the SATA II 1.2 spec. Notably, this documents Native Command Queueing (NCQ), asynchronous notification (eliminates CD-ROM polling), and other features.
The only other really interesting spec (at this time) is the Port Multiplier spec. Port Multipliers allow several disks to be attached to a single SATA port, rather than just one.
To say that ATAPI is "interesting" would be an understatement. The ATA packet interface (ATAPI) evolved from SFF 8020i into the SCSI MMC standards published on the T10 committee website. ATAPI is not SCSI, although
- it is suspiciously similar to SCSI, and
- to further confuse matters, compliant SCSI-2/3 devices are sometimes connected to the ATA bus via the ATA packet interface
Relevant standards are MMC, MMC-2, MMC-3, MMC-4, MMC-5. Although most folks desperately want SFF 8020i to disappear ("it's dead, Jim"), it is unfortunately still needed as a reference when working with ancient ATAPI devices still in circulation.
ATA/ATAPI host controllers
Prior to the introduction of SATA, the vast majority of ATA host controllers simply provided direct access to the ATA shadow registers, and some vendor-specific method of controlling DMA.
First-generation SATA controllers follow this design as well, usually because the chips were implemented by gluing an existing PATA chip to a PATA<->SATA bridge chip. Thus, many SATA controller designs mimic PATA, with a single additional register block for controlling the SATA PHY.
More recent SATA controllers such as AHCI are much more high level, typically implementing an asynchronous DMA interface (DMA ring, array, or linked list) for all ATA commands. Given that SATA data is broken up into a packet called a "FIS", most new SATA controllers are FIS-based, requiring an OS driver to be able to build, and understand, a SATA FIS structure.
The classical ATA shadow register interface, with PCI-specific DMA extensions, is documented in the ATA Host Adapter Standards spec. This document also describes a newer and far less common "ADMA" host controller interface. This document describes a PATA host controller interface, but many first-gen SATA controllers chose to continue use of this interface for legacy compatibility reasons. This interface was originally described in SFF 8038i (link anyone?).
An example of the newer FIS-based architecture can be found in the AHCI 1.0 spec. This is the interface being implemented by most of the major motherboard chipset vendors (Intel, VIA, SiS, ULi, others?). The AHCI design is far more efficient than the traditional ATA shadow register interface, on modern computers.
Full list of public ATA controller specs: